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MOSEL VITELIC
V53C8256H ULTRA-HIGH SPEED, 256K x 8 FAST PAGE MODE CMOS DYNAMIC RAM
PRELIMINARY
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Fast Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
35
35 ns 18 ns 21 ns 70 ns
40
40 ns 20 ns 23 ns 75 ns
45
45 ns 22 ns 25 ns 80 ns
50
50 ns 24 ns 28 ns 90 ns
Features
s 256K x 8-bit organization s Fast Page Mode for a sustained data rate of 47 MHz s RAS access time: 35, 40, 45, 50 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh capability s Refresh Interval: 512 cycles/8 ms s Single 5V 10% Power Supply s Available in 24-pin 300 mil Plastic DIP, 26/24-pin 300 mil SOJ, and 28-pin TSOP-I packages
Description
The V53C8256H is a high speed 262,144 x 8 bit CMOS dynamic random access memory. The V53C8256H offers a combination of features: Fast Page Mode for high data bandwidth, fast usable speed, CMOS standby current. All inputs and outputs are TTL compatible. Input and output capacitances are significantly lowered to allow increased system performance. Fast Page Mode operation allows random access of up to 512 (x8) bits within a row with cycle times as short as 21 ns. Because of static circuitry, the CAS clock is not in the critical timing path. The flow-through column address latches allow address pipelining while relaxing many critical system timing requirements for fast usable speed. These features make the V53C8256H ideally suited for graphics, digital signal processing and high performance computing systems.
Device Usage Chart
Operating Temperature Range
0C to 70 C
Package Outline P
*
Access Time (ns) T
*
Power 50
*
K
*
35
*
40
*
45
*
Std.
*
Temperature Mark
Blank
V53C8256H Rev. 1.4 February 1999
1
MOSEL VITELIC
V 5 3 C 8 2 5 6 H
V53C8256H
FAMILY
DEVICE
PKG
SPEED ( t RAC)
TEMP. PWR. BLANK (0C to 70C) BLANK (NORMAL) 35 40 45 50 (35 ns) (40 ns) (45 ns) (50 ns)
Description Plastic DIP SOJ TSOP-I
Pkg. P K T
Pin Count 24 26/24 28
P (PLASTIC DIP) K (SOJ) T (TSOP-I)
8256H-01
24-Pin Plastic DIP PIN CONFIGURATION Top View
VSS I/O1 I/O2 I/O3 I/O4 WE RAS A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
26/24-Pin SOJ PIN CONFIGURATION Top View
VSS I/O1 I/O2 I/O3 I/O4 WE RAS A0 A1 A2 A3 VDD
1 2 3 4 5 6 8 9 10 11 12 13 27 26 24 23 22 21 19 18 17 16 15 14
VSS I/O8 I/O7 I/O6 I/O5 CAS OE A8 A7 A6 A5 A4
300 mil
300 mil
VSS I/O8 I/O7 I/O6 I/O5 CAS OE A8 A7 A6 A5 A4
8256H-02
8256H-03
28-Pin TSOP-I PIN CONFIGURATION Top View
CAS I/O5 I/O6 I/O7 I/O8 VSS VSS NC I/O1 I/O2 I/O3 I/O4 NC WE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
8258H-04
Pin Names
A0-A8 RAS
OE A8 A7 A6 A5 A4 NC VCC NC A3 A2 A1 A0 RAS
Address Inputs Row Address Strobe Column Address Strobe Write Enable Output Enable Data Input, Output +5V Supply 0V Supply No Connect
CAS WE OE I/O1-I/O8 VDD VSS NC
V53C8256H Rev. 1.4 February 1999
2
MOSEL VITELIC
Absolute Maximum Ratings*
Ambient Temperature Under Bias .............................. -10C to +80C Storage Temperature (plastic) ...... -55C to +125C Voltage Relative to VSS ...................-1.0V to +7.0V Data Output Current ..................................... 50 mA Power Dissipation .......................................... 1.0 W
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
V53C8256H
TA = 25C, VDD = 5 V 10%, VSS = 0 V
Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, WE, OE Data Input/Output Min. 3 4 5 Max. 4 5 7 Unit pF pF pF
Capacitance*
*Note: Capacitance is sampled and not 100% tested.
Block Diagram
256K x 8
OE WE CAS RAS
RAS CLOCK GENERATOR
CAS CLOCK GENERATOR
WE CLOCK GENERATOR
OE CLOCK GENERATOR
VDD VSS
DATA I/O BUS COLUMN DECODERS
Y0 -Y8
I/O 1 I/O 2 I/O 3
SENSE AMPLIFIERS
512 x 8
I/O BUFFER
I/O 4 I/O 5 I/O 6 I/O 7 I/O 8
REFRESH COUNTER
9 A0 A1
ADDRESS BUFFERS AND PREDECODERS
X 0 -X8
ROW DECODERS
512
* * *
A 7 A8
MEMORY ARRAY
8256H-05
V53C8256H Rev. 1.4 February 1999
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MOSEL VITELIC
DC and Operating Characteristics (1-2) TA = 0C to 70C, VCC = 5 V 10%, VSS = 0 V, unless otherwise specified.
V53C8256H Symbol ILI ILO ICC1 Parameter Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) VCC Supply Current, Operating 35 40 45 50 ICC2 ICC3 VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh 35 40 45 50 ICC4 VCC Supply Current, Fast Page Mode Operation 35 40 45 50 ICC5 ICC6 VCC Supply Current, Standby, Output Enabled VCC Supply Current, CMOS Standby Access Time Min. -10 Typ. Max. 10 Unit A A mA
V53C8256H
Test Conditions VSS VIN VCC VSS VOUT VCC RAS, CAS at VIH tRC = tRC (min.)
Notes
-10
10
160 150 145 135 4
1, 2
mA
RAS, CAS at VIH other inputs VSS tRC = tRC (min.) 2
160 150 145 135 95 90 85 80 2
mA
mA
Minimum Cycle
1, 2
mA
RAS = VIH, CAS = VIL, other inputs VSS RAS VCC - 0.2 V, CAS VCC - 0.2 V, All other inputs VSS
1
1
mA
VIL VIH VOL VOH
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
-1 2.4
0.8 VCC + 1 0.4
V V V V IOL = 4.2 mA IOH = -5 mA
3 3
2.4
V53C8256H Rev. 1.4 February 1999
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MOSEL VITELIC
AC Characteristics
TA = 0C to 70C, VCC = 5 V 10%, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V
35 # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 JEDEC Symbol tRL1RH1 tRL2RL2 tRH2RL2 tRL1CH1 tCL1CH1 tRL1CL1 tWH2CL2 tAVRL2 tRL1AX tAVCL2 tCL1AX tCL1RH1(R) tCH2RL2 tCH2WX tRH2WX tOEL1RH2 tGL1QV tCL1QV tRL1QV tAVQV tCL1QX tCH2QZ tRL1AX tRL1AV tCL1RH1(W) tWL1CH1 tWL1CL2 tCL1WH1 Symbol tRAS tRC tRP tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH tRSH (R) tCRP tRCH tRRH tROH tOAC tCAC tRAC tCAA tLZ tHZ tAR tRAD tRSH (W) tCWL tWCS tWCH Parameter RAS Pulse Width Read or Write Cycle Time RAS Precharge Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time RAS Hold Time (Read Cycle) CAS to RAS Precharge Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS RAS Hold Time Referenced to OE Access Time from OE Access Time from CAS Access Time from RAS Access Time from Column Address OE or CAS to Low-Z Output OE or CAS to High-Z Output Column Address Hold Time from RAS RAS to Column Address Delay Time RAS or CAS Hold Time in Write Cycle Write Command to CAS Lead Time Write Command Setup Time Write Command Hold Time 0 0 28 6 40 45 50
V53C8256H
Min. Max. Min. Max. Min. Max. Min. Max. Unit 35 70 25 35 12 16 0 0 6 0 4 12 5 0 23 75K 40 75 25 40 12 17 0 0 7 0 5 12 5 0 28 75K 45 80 25 45 13 18 0 0 8 0 6 13 5 0 32 75K 50 90 30 50 14 19 0 0 9 0 7 14 5 0 36 75K ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes
4
5
15
0
0
0
0
ns
5
16
8
8
9
10
ns
17 18 19 20
12 12 35 18
12 12 40 20
13 13 45 22
14 14 50 24
ns ns ns ns 6, 7 6, 8, 9 6, 7, 10
21 22 23
0 0 30 6
0 0 35 7
0 0 40 8
ns ns ns
16 16
24
11
17
12
20
13
23
14
26
ns
11
25
12
12
13
14
ns
26
12
12
13
14
ns
27 28
0 5
0 5
0 6
0 7
ns ns
12, 13
V53C8256H Rev. 1.4 February 1999
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MOSEL VITELIC
AC Characteristics (Cont'd)
35 # 29 30 JEDEC Symbol tWL1WH1 tRL1WH1 tWL1RH1 tDVWL2 tWL1DX tWL1GL2 tGH2DX tRL2RL2 (RMW) tRL1RH1 (RMW) tCL1WL2 tRL1WL2 tCL1CH1 tAVWL2 tCL2CL2 tCH2CL2 tAVRH1 tCH2QV tRL1DX tCL1RL2 tRH2CL2 tRL1CH1 tCL2CL2 (RMW) tT Symbol tWP tWCR tRWL tDS tDH tWOH tOED tRWC tRRW tCWD tRWD tCRW tAWD tPC tCP tCAR tCAP tDHR tCSR tRPC tCHR tPCM tT tREF Parameter Write Pulse Width Write Command Hold Time from RAS Write Command to RAS Lead Time Data in Setup Time Data in Hold Time Write to OE Hold Time OE to Data Delay Time Read-Modify-Write Cycle Time 40 45 50
V53C8256H
Min. Max. Min. Max. Min. Max. Min. Max. Unit 5 28 5 30 6 35 7 40 ns ns
Notes
31
12
12
13
14
ns
32 33 34 35 36
0 4 5 5 105
0 5 6 6 110
0 6 7 7 115
0 7 8 8 130
ns ns ns ns ns
14 14 14 14
37
Read-Modify-Write Cycle RAS Pulse Width CAS to WE Delay RAS to WE Delay in ReadModify-Write Cycle CAS Pulse Width (RMW) Col. Address to WE Delay Fast Page Mode CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge Data in Hold Time Referenced to RAS CAS Setup Time CAS-before-RAS Refresh RAS to CAS Precharge Time CAS Hold Time CAS-before-RAS Refresh Fast Page Mode Read-ModifyWrite Cycle Time Transition Time (Rise and Fall) Refresh Interval (512 Cycles)
70
75
80
87
ns
38 39
28 54
30 58
32 62
34 68
ns ns
12 12
40 41 42 43 44
46 35 21 4 18
48 38 23 5 20
50 41 25 6 22
52 42 28 7 24
ns ns ns ns ns 12
45
20
22
24
27
ns
7
46
28
30
35
40
ns
47
10
10
10
10
ns
48 49
0 8
0 8
0 10
0 12
ns ns
50
58
60
65
70
ns
3
50 8
3
50 8
3
50 8
3
50 8
ns ms
15 17
V53C8256H Rev. 1.4 February 1999
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MOSEL VITELIC
Notes:
V53C8256H
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two transitions per address cycle in Fast Page Mode. 3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to -1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) VSS and VIH (max.) VCC. 4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. 5. Either tRRH or tRCH must be satisified for a Read Cycle to occur. 6. Measured with a load equivalent to two TTL inputs and 50 pF. 7. Access time is determined by the longest of tCAA, tCAC and tCAP. 8. Assumes that tRAD tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). 9. Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds tRCD (max.). 10. Assumes that tRAD tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns. 16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent). 17. An initial 200 s pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C8256H Rev. 1.4 February 1999
7
MOSEL VITELIC
Waveforms of Read Cycle
t RC (2) t RAS (1) RAS VIH VIL t CSH (4) t CRP (13) CAS VIH VIL tASR (8) ADDRESS VIH VIL ROW ADDRESS t RAD (24) t RAH (9) t ASC (10) COLUMN ADDRESS t CAR (44) t RCS (7) WE VIH VIL t CAA (20) OE VIH V IL t CAC (18) tRAC (19) I/O VOH VOL t LZ (21) t HZ (22) VALID DATA-OUT tOAC (17) t ROH (16) t ROH (15) t CAH (11) t RCD (8) t RSH (R)(12) t CAS (5) tAR (23) t RP (3)
V53C8256H
t CRP (13)
t RCH (14)
tHZ (22)
8256H-06
Waveforms of Early Write Cycle
t RC (2) t RAS (1) RAS VIH V IL t CSH (4) tCRP (13) VIH CAS V IL t RAH (9) tASR (8) ADDRESS VIH V IL ROW ADDRESS t RAD (24) t CWL (26) VIH V IL t WCR (30) t RWL (31) OE VIH V IL t DHR (46) tDS (32) I/O VIH V IL tDH (33) VALID DATA-IN HIGH-Z
8256H-07
t RP (3)
tAR (23)
t RCD (6)
t RSH (W)(25) t CAS (5)
t CRP (13)
t CAR (44) t CAH (11) tASC (10)
COLUMN ADDRESS t WCH (28) t WP(29) tWCS (27)
WE
Don't Care
V53C8256H Rev. 1.4 February 1999
Undefined
8
MOSEL VITELIC
Waveforms of Write Cycle (OE Controlled Write)
t RC (2) tRAS (1) RAS VIH V IL t CRP (13) VIH CAS V IL tRAD (24) t RAH (9) tASR (8) ADDRESS VIH V IL ROW ADDRESS tASC (10) COLUMN ADDRESS t CWL (26) t RWL (31) t WP(29) WE VIH V IL t WOH (34) OE VIH V IL t OED (35) VIH V IL tDH (33) t DS (32) VALID DATA-IN t CAR (44) t CAH (11) t CSH (4) t RCD (6) t RSH (W)(12) tCAS (5) t AR (23) t RP (3)
V53C8256H
t CRP (13)
I/O
8256H-09
Waveforms of Read-Modify-Write Cycle
tRWC (36) tRRW (37) RAS V IH VIL t CSH (4) t CRP (13) VIH CAS VIL tRAH (9) tASR (8) ADDRESS VIH VIL ROW ADDRESS t RAD (24) tRWD (39) WE VIH VIL VIH VIL t OED (35) tCAC (18) tRAC (19) I/O VIH VIL VOH VOL tLZ (21) VALID DATA-OUT tHZ (22) t DS (32) VALID DATA-IN
8256H-09
tRP (3)
tAR (23)
tRCD (6)
tRSH (W)(25) t CRW (40) tCAH (11) tASC (10) COLUMN ADDRESS tAWD (41) tCWD (38) t CWL (26) tRWL (31) tWP(29)
tCRP (13)
t CAA (20) t OAC (17)
OE
tDH (33)
Don't Care
V53C8256H Rev. 1.4 February 1999
Undefined
9
MOSEL VITELIC
Waveforms of Fast Page Mode Read Cycle
RAS VIH V IL t RCD (6) tCRP (13) CAS VIH V IL t RAH (9) tCSH (4) tASC (10) t CAH (11) COLUMN ADDRESS COLUMN ADDRESS t RCH (14) t CAH (11) t RCS (7) COLUMN ADDRESS t RCS (7) tCAR (44) tPC (42) tCP(43) tRSH (R)(12) tCAS (5) t CRP (13) t CAS (5) tAR (23) t RAS (1)
V53C8256H
t
RP (3)
t CAS (5)
tASR (8) ADDRESS VIH V IL
tASC (10) ROW ADDRESS t RCS (7)
t CAH (11)
tRCH (14)
WE
VIH V IL tCAA (20) t OAC (17) t CAP (45) t OAC (17) t CAA (20) t OAC (17) tRRH (15)
OE
VIH V IL tHZ (22) tRAC (19) tCAC (18) t LZ (21) tCAC (18) t HZ (22) t LZ (21) VALID DATA OUT t LZ (21) tHZ (22) tHZ (22) V ALID DATA OUT VALID DATA OUT
8256H-10
t CAC (18)
tHZ (22) tHZ (22)
I/O
VOH VOL
Waveforms of Fast Page Mode Write Cycle
tAR (23) RAS VIH V IL t CRP (13) tRCD (6) CAS VIH V IL tCSH (4) tRAH (9) t ASR (8) ADDRESS VIH V IL tRAD (24) t WCS (27) t WP (29) WE VIH V IL VIH VIL t DS (32) I/O VIH V IL
VALID DATA IN ROW ADD COLUMN ADDRESS
tRP (3) t RAS (1)
t PC (42) t CP(43) t CAS (5)
t RSH (W)(25) t CRP (13) tCAS (5) tCAS (5)
t CAR (44) tASC (10) tCAH (11)
COLUMN ADDRESS
tASC (10) tCAH (11)
COLUMN ADDRESS
t CAH (11)
t CWL (26) t WCS (27) t WCH (28)
t CWL (26) t WCS (27) t WCH (28) t WP(29)
tCWL (26) tRWL(31) t WCH (28) tWP(29)
OE
tDS (32) t DH (33)
OPEN VALID DATA IN
tDS (32) tDH (33)
VALID DATA IN
tDH (33)
OPEN
8256H-11
Don't Care
V53C8256H Rev. 1.4 February 1999
Undefined
10
MOSEL VITELIC
Waveforms of Fast Page Mode Read-Write Cycle
RAS VIH V
IL
V53C8256H
tRAS (1)
t CSH (4) tRCD (6) tPCM (50) t CP(43) V CAS V
IH IL
tRP (3) t RSH (W)(25) t CRP (13) t CAS (5)
t CAS (5) t RAD (24) tRAH (9) tASC (10) tASR (8) tASC (10) tCAH (11)
COLUMN ADDRESS COLUMN ADDRESS
t CAS (5)
t CAR (44) tASC (10) tCAH (11)
COLUMN ADDRESS
t CAH (11)
V ADDRESS V
IH IL
ROW ADD
tRWD (39) t RCS (7) t CWD (38) V WE V
IH IL
tCWD (38) t CWL (26) t CWL (26)
t CWD (38) tRWL(31) tCWL (26)
tAWD (41) t CAA (20) t OAC (17) V OE V
IH IL
tAWD (41) t WP(29) t OAC (17)
tAWD (41) tWP(29) t OAC (17) tWP(29)
tCAP (45) tOED (35) t CAC (18) t RAC (19) t CAA (20) tOED (35) t CAC (18) tHZ (22)
tCAP (45) t CAA (20) t OED (35) tCAC (18) t HZ (22) tDH (33) tDS (32)
OUT IN
8256H-12
t HZ (22) tDH (33) t DH (33) tDS (32)
OUT IN
tDS (32) I/O VI/OH VI/OL t LZ (21)
OUT IN
tLZ (21)
tLZ (21)
Waveforms of RAS Only Refresh Cycle
t RC (2) V IH V IL t CRP (13) CAS V IH V IL t ASR (8) ADDRESS V IH V IL NOTE: ROW ADDR
8256H-13
t RAS (1)
t RP (3)
RAS
t RAH (9)
WE, OE = Don't care
Don't Care
V53C8256H Rev. 1.4 February 1999
Undefined
11
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1) RAS VIH V IL t CSR (47) CAS VIH V IL VIH V IL READ CYCLE VIH V IL t ROH (16) t OAC (17) OE VIH V IL t LZ (21) I/O VIH V IL WRITE CYCLE VIH V IL VIH V IL tDS (32) I/O VIH V IL t DH (33) D IN t RWL (31) t CWL (26) t WCS (27) t WCH (28) DOUT t CHR (49) t CP(43) t RSH (W)(25) tCAS (5)
V53C8256H
t RP (3)
ADDRESS
t RCS (7)
t RRH (15) t RCH (14)
WE
t HZ (22) t HZ (22)
WE
OE
8256H-14
Waveforms of CAS-before-RAS Refresh Cycle
t RC (2) t RP (3) RAS VIH V IL t CP (43) t CSR (47) CAS VIH V IL t HZ (22) I/O VOH VOL NOTE: WE, OE, A0-A7 = Don't care
8256H-15
t RAS (1)
t RP (3)
t RPC (48) t CHR (49)
Don't Care
V53C8256H Rev. 1.4 February 1999
Undefined
12
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
tRC (2) VIH V IL tRCD (6) t CRP (13) VIH CAS V IL tASR (8) t RAH (9) ADDRESS VIH V IL VIH V IL t CAA (20) t OAC (17) OE VIH V IL t CAC (18) t LZ (21) t RAC (19) I/O VOH VOL VALID DATA t HZ (22) t HZ (22)
ROW ADD
V53C8256H
tRC (2) t RP (3) t RAS (1) t RP (3)
t RAS (1) tAR (23)
RAS
tRSH (R)(12)
t CHR (49)
tCRP (13)
tRAD (24) tASC (10) t CAH (11)
COLUMN ADDRESS
tRCS (7) WE
t RRH (15)
8256H-16
Waveforms of Hidden Refresh Cycle (Write)
t RC (2) VIH RAS V IL t RCD (6) t CRP (13) CAS VIH V IL tASR (8) t RAH (9) ADDRESS VIH V IL VIH V IL VIH OE V IL t DS (32) VIH I/O V IL tDH (33)
VALID DATA-IN ROW ADD
t RC (2) tRP (3) t RAS (1) tRP (3)
t RAS (1) tAR (23)
t RSH (12)
t CHR (49)
t CRP (13)
tRAD (24) tASC (10) t CAH (11)
COLUMN ADDRESS
t WCS (27) WE
t WCH (28)
t DHR (46)
8256H-17
Don't Care
V53C8256H Rev. 1.4 February 1999
Undefined
13
MOSEL VITELIC
Functional Description
The V53C8256H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C8256H reads and writes data by multiplexing an 18-bit address into a 9-bit row and a 9-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address "flows through" an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time.
V53C8256H
Refresh Cycle
To retain data, 512 Refresh Cycles are required in each 8 ms period. There are two ways to refresh the memory: 1. By clocking each of the 512 row addresses (A0 through A8) with RAS at least once every 8 ms. Any Read, Write, Read-Modify-Write or RASonly cycle refreshes the addressed row. 2. Using a CAS-before-RAS Refresh Cycle. If CAS makes a transition from low to high to low after the previous cycle and before RAS falls, CASbefore-RAS refresh is activated. The V53C8256H uses the output of an internal 9-bit counter as the source of row addresses and ignore external address inputs. CAS-before-RAS is a "refresh-only" mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. A CAS-before-RAS counter test mode is provided to ensure reliable operation of the internal refresh counter.
Memory Cycle
A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP/tCP has elapsed.
Read Cycle
A Read cycle is performed by holding the Write Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC, tRAC, tCAA and tCAC are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied.
Fast Page Mode Operation
Fast Page Mode operation permits all 512 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer and acts as an output enable. During Fast Page Mode operation, Read, Write, Read-Modify-Write or ReadWrite-Read cycles are possible at random addresses within a row. Following the initial entry cycle into Fast Page Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA. In both cases, the falling edge of CAS latches the address and enables the output.
Write Cycle
A Write Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied.
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Fast Page Mode provides a sustained data rate of 47 MHz for applications that require high data rates such as bit-mapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: 512 Data Rate = ---------------------------------------t RC + 511 x t PC
V53C8256H
During Power-On, the VDD current requirement of the V53C8256H is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and IDD will exhibit current transients. It is recommended that RAS and CAS track with VDD or be held at a valid VIH during Power-On to avoid current surges.
Table 1. V53C8256H Data Output Data Output Operation
The V53C8256H Input/Output is controlled by OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition or CAS low level enables the internal I/O path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The OE signal has no effect on any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE goes low at a time in relationship to CAS that would normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to the WE low transition to allow Data In Setup Time (tDS) to be satisfied. Operation for Various Cycle Types
Cycle Type
Read Cycles CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) Read-Modify-Write Cycles Fast Page Mode Read Cycle Fast Page Mode Write Cycle (Early Write) Fast Page Mode ReadModify-Write Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle CAS-only Cycles
I/O State
Data from Addressed Memory Cell High-Z OE Controlled. High OE = High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z Data from Addressed Memory Cell High-Z Data remains as in previous cycle High-Z
Power-On
After application of the VDD supply, an initial pause of 200 s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval).
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Package Diagrams
24-Pin 300 mil PDIP
V53C8256H
0.300 - 0.330 [7.62 - 8.38] 0.250 - 0.300 [6.35 - 7.62]
Unit in inches [mm]
1.310 Max. [33.27 Max.] 0.005 - 0.050 [0.127 - 1.27]
.180 Max. [4.57 Max.]
0.110 - 0.140 [2.79 - 3.56] .100 Typ. [2.54 Typ.] 0.048 - 0.065 [1.22 - 1.65] 0.018 - 0.024 [0.457 - 0.610] 0.320 - 0.390 [8.13 - 9.91]
.008 - .013 [.203 - .330]
26/24-Pin 300 mil SOJ
0.332 - 0.342 [8.43 - 8.69] 0.296 - 0.304 [7.52 - 7.72]
Unit in inches [mm]
0.665 - 0.698 [16.89 - 17.73] 0.082 - 0.093 [2.08 - 2.36] 0.028 Typ. [0.711 Typ.] 0.05 Typ. [1.27 Typ.] 0.125 - 0.135 [3.175 - 3.429]
0.018 Typ. [0.457 Typ.]
0.025 Min. [0.635 Min.]
0.255 - 0.275 [6.477 - 6.985]
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28-Pin TSOP-I
V53C8256H
Unit in inches .035 - .043 .039 DIA. Pin # 1 I.D. .520 - .535 .461 - .469 .035 - .043 .022 .311 - .319 C.O.O. denotes country of orgin .047 Detail "A" .004 .002 - .006 .000 .079 DIA. x .004 Deep Fixed Pin (1 Plcs.)
.022
.055 - .063 .010 Top View .022 D .037 - .041 See Detail "A" D .007 - .011 .007 - .009 With Plating .020 - .028 .004 - .008 0.25 BSC Detail "B" 0 - 6 .08 - .20 Gage Plane .012 MAX Bottom View See Detail "B" .055 - .063
Base Metal
.004 - .006
Detail "A"
Section "D-D"
V53C8256H Rev. 1.4 February 1999
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MOSEL VITELIC
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
WORLDWIDE OFFICES
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-578-3344 FAX: 886-3-579-2838
V53C8256H
IRELAND & UK
BLOCK A UNIT 2 BROOMFIELD BUSINESS PARK MALAHIDE CO. DUBLIN, IRELAND PHONE: +353 1 8038020 FAX: +353 1 8038049
SINGAPORE
10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013
HONG KONG
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JAPAN
WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 81-43-299-6000 FAX: 81-43-299-6555
GERMANY (CONTINENTAL EUROPE & ISRAEL )
71083 HERRENBERG BENZSTR. 32 GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
NORTHEASTERN
SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347
SOUTHWESTERN
SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 562-498-3314 FAX: 562-597-2174
CENTRAL & SOUTHEASTERN
604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341
NORTHEASTERN
SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347
(c) Copyright 1999, MOSEL VITELIC Inc.
2/99 Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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